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ISL6209
A good layout would help reduce the ringing on the phase
and gatenodes significantly:
1. Avoid using vias for decoupling components where
possible, especially in the BOOT-to-PHASE path. Little or
no use of vias for VCC and GND is also recommended.
Decoupling loops should be short.
2. All power traces (UGATE, PHASE, LGATE, GND, VCC)
should be short and wide, and avoid using vias. If vias
must be used, two or more vias per layer transition is
recommended.
3. Keep the SOURCE of the upper FET as close as
thermally possible to the DRAIN of the lower FET.
4. Keep the connection in between the SOURCE of lower
FET and power ground wide and short.
5. Input capacitors should be placed as close to the DRAIN
of the upper FET and the SOURCE of the lower FET as
thermally possible.
NOTE: Refer to Intersil Tech Brief TB447 for more information.
Thermal Management
For maximum thermal performance in high current, high
switching frequency applications, connecting the thermal
pad of the QFN part to the power ground with multiple vias,
or placing a low noise copper plane underneath the SOIC
part is recommended. This heat spreading allows the part to
achieve its full thermal potential.
Suppressing MOSFET Gate Leakage
With VCC at ground potential, UGATE and LGATE are high
impedance. In this state, any stray leakage has the potential
to deliver charge to either gate. If UGATE receives sufficient
charge to bias the device on (Note: Internal circuitry prevents
leakage currents from charging above 1.8V), a low
impedance path will be connected between the MOSFET
drain and PHASE. If the input power supply is present and
active, the system could see potentially damaging currents.
Worst-case leakage currents are on the order of pico-amps;
therefore, a 10k Ω resistor, connected from UGATE to
PHASE, is more than sufficient to bleed off any stray leakage
current. This resistor will not affect the normal performance
of the driver or reduce its efficiency.
8
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